library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity shifter is
generic(	N       	:     natural := 32;
		N_SHAMT :     natural := 5 );
port(	ARITH	: in   std_logic;    		-- '1' means arithmetic shift, '0' means logical shift
		DIR		: in   std_logic;     		-- '0' means left shift, '1' means right shift
		D_IN	: in   std_logic_vector (N-1 downto 0);
		SHAMT	: in   std_logic_vector (N_SHAMT-1 downto 0);
		D_OUT	: out std_logic_vector (N-1 downto 0)
        );
end shifter;

architecture Behavioral of shifter is
	signal amt : natural range 0 to N-1;
begin
	amt <= to_integer(unsigned(SHAMT));

process (D_IN, amt, ARITH, DIR)
begin
	if DIR = '0' then			--left shift    
		for i in N - 1 downto 0 loop
			if i >= amt then
				D_OUT (i)   <= D_IN(i-amt);
			else
				D_OUT (i)   <= '0';
			end if;
		end loop;
	else						--right shift
		for i in 0 to N-1 loop
			if i <= (N-1-amt) then
				D_OUT (i)   <= D_IN(i+amt);
			else
			-- if ARITH='1' the sign extension is done, otherwise all zeros are inserted from the left
				D_OUT (i) <= D_IN(N-1) and ARITH;
			end if;
		end loop;
	end if; -- end DIR

end process;

end Behavioral;
